1. Field of the Invention
The present invention relates to semiconductor technologies, in particular, to a method for improving the yield of a fin field effect transistor (FinFET).
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various Fin-shaped field effect transistor (FinFET) devices have been developed. The Fin-shaped field effect transistor (FinFET) is advantageous for the following reasons. First, manufacturing processes of Fin-shaped field effect transistor (FinFET) devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the FinFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
In a current FinFET process, agate structure (which may include a gate dielectric layer, a gate electrode located on the gate dielectric layer, a cap layer located on the gate electrode, and a spacer located beside the gate dielectric layer, the gate electrode and the cap layer) is formed on a substrate having at least a fin-shaped structure. Then, epitaxial layers are formed on the fin-shaped structure beside the gate structure. Thereafter, other processes such as removing spacers of the gate structure may be performed.
However, the epitaxial layers make removal of the spacers difficult. The distance between the epitaxial layers on either side of the gate structure is also too great, resulting in insufficient stress forcing the gate channel below the gate structure, and limited ability to enhance carrier mobility of the gate channel through the epitaxial layers.
U.S. Pat. No. 7,435,683 provides a method for forming a semiconductor structure, and the semiconductor structures are shown in FIGS. 1-3. Firstly, a substrate 10 is provided, a fin structure 12 is formed on the substrate 10. Next, a gate structure 14 is formed on the fin structure 12, and a hard mask 16 is further formed on the top surface gate structure 14. Afterward, a dielectric layer 18 is formed to entirely cover the fin structure 12, the gate structure 14, and the hard mask 16.
Next, as shown in FIG. 2, an etching back process is performed, to partially remove the dielectric layer 18, and to expose the top surface and parts of the sidewall of the hard mask 16. Afterwards, a hard mask 20 is conformally formed to cover the surface of the dielectric layer 18, and further cover the top surface and partial sidewall of the hard mask 16.
Afterwards, as shown in FIG. 3, an etching process is performed, such as an anisotropic dry etching process, to remove parts of the hard mask 20, so as to form a sail shaped spacer 22 on the dielectric layer 18. The spacer 22 can protect the elements dispose below, especially preventing the gate structure 14 from being destroyed during the etching process in the following steps. Next, the spacer 22 is used as the hard mask, and another etching process is performed to partially remove the dielectric layer 18, and a spacer 24 is formed, covering two sidewalls of the gate structure 14. It is noteworthy that the spacer 24 is a truncated-sail shaped structure, and the epitaxial layer (not shown) is then formed on two sides of the gate structure in the following steps. It will not be described in detail here.
The method mentioned above can remove the dielectric layer which remains beside the epitaxial layer clearly. However, the thickness of the spacer 24 which is disposed on two sides of the gate structure is still influenced by the thickness of the spacer 22, and cannot be controlled well. Therefore, the method mentioned above still needs be improved.